As the critical dimension of metal oxide semiconductor field effect transistor (MOSFET) devices continues to shrink, the short channel effect becomes more problematic. Fin field effect transistor (FinFET) devices have better control capability of gates than planar MOSFET devices to effectively suppress the short channel effect. Gate-all-around (GAA) devices have even better control ability than FinFET devices to more effectively suppress the short channel effect.
A nanowire vertical transistor is an example of a GAA device.
In some conventional methods of manufacturing nanowire vertical transistors, after nanowires 102 are formed on a substrate 101, a contact material 103 is then formed on substrate 101 and on upper surfaces of nanowires 102 by an anisotropic deposition, as shown in FIG. 1A. However, contact material 103 is inevitably formed on sidewalls of nanowires 102, thereby reacting with nanowires 102 to form a metal silicide. The presence of the metal silicide affects the channel performance of nanowires, thereby affecting the performance of nanowire vertical transistors.
In some other conventional methods of manufacturing a nanowire vertical transistor, after nanowires 102 are formed on a substrate 101, a gate dielectric layer 104 is formed on sidewalls of nanowires 102. A contact material 103 is formed on substrate 101 and on upper surfaces of nanowires by an anisotropic deposition, as shown in FIG. 1B. This method may prevent contact material 103 from being formed on the sidewalls of nanowires 102. Since contact material 103 does not come into contact with the bottom of nanowires 102, a metal silicide 105 is only formed in substrate 101 but not at the bottom of nanowires 102, this will increase the series resistance of a source.
Therefore, there is a need for improved methods for manufacturing a fin-type semiconductor device to overcome these drawbacks.